Logic Design Engineer

Feladatok: Designing a configurable and very low-latency challenging RTLBringing the state-of-the-art FPGA to its limits with regards to logic & timing optimizationEnd2end ownership of the entire coding process (Arch->uArch->Design->Implementation)Learning system and SW requirements for proper implementation of HW-SW interface Elvárások: Designing a configurable and very low-latency challenging RTLBringing the state-of-the-art FPGA to its limits with regards to logic & timing optimizationEnd2end ownership of the entire coding process (Arch->uArch->Design->Implementation)Learning system and SW requirements for proper implementation of HW-SW interfaceGépészmérnök